The present invention relates to a manufacturing method of semiconductor device provided with a plurality of embedded wiring and/or through holes.
A formation method of conventional embedded wiring is explained referring to FIGS. 1A to 1D.
Firstly, as shown in FIG. 1A, silicone nitride film 2 (film thickness 100 nm) and silicone oxide film 3 (film thickness 1000 nm) are formed on silicone substrate 1 in order. Next, a plurality of holes which come to the silicone nitride film 2 are formed within the silicone oxide film 3 using dry etching.
Next, as shown in FIG. 1B, the manufacturing process deposits barrier metal layer 4 consisting of titanium xe2x80x98Tixe2x80x99 and titanium nitride xe2x80x98TiNxe2x80x99 all over the surface thereof by sputtering method. Film-thickness thereof is 200 xc3x85. Continuously, the manufacturing process deposits seed metal layer consisting of copper thereon by sputtering method for growing copper plating (not illustrated). Further, uninterruptedly, the manufacturing process immerses the silicone substrate 1 into copper sulfate aqueous solution with solution temperature about 25xc2x0 C., to form metal plating layer 5 consisting of copper by electrolytic plating method. A power-supply for forming the plating, for instance, uses direct current power-supply, setting with current value as 0.5 A/dm2. Here, layer thickness of metal plating layer 5 is set to approximately 900 nm in flat part. Status thereof is indicated in FIG. 1B.
The manufacturing process implements annealing about the substrate subjected to plating as mentioned above, in such a way as degree of 30 minutes with 300xc2x0 C. Due to this annealing, grain-size grows larger and resistance value is lowered.
Subsequently, the manufacturing process polishes the metal plating layer 5 by xe2x80x98CMPxe2x80x99 (Chemical Mechanical Polishing) to make surface of the substrate flat, thus causing embedded wiring is perfected (FIGS. 1C, 1D).
However, above-described prior art involves following problems:
In manufacturing process of xe2x80x98CMPxe2x80x99 shown in FIGS. 1C, 1D, it is necessary to take a large amount of time for polishing such that the metal plating layer 5 on the silicone oxide layer 3 does not rest. Here, polishing speed in relation to the metal plating layer 5 is large in comparison with polishing speed in relation to the barrier metal layer 4 or the silicone oxide layer 3. For that reason, in the manufacturing process of xe2x80x98CMPxe2x80x99 after exposure of the barrier metal layer 4, wiring dense part in which a lot of embedded parts of the metal plating layer 5 exist is added high pressure on the barrier metal layer 4 and/or the silicone oxide layer 3 in comparison with wiring isolated part in which embedded part of the metal plating film exists not so many. For that reason, xe2x80x98CMPxe2x80x99 is progressed in excess at the wiring dense part, thus problem occurs that surface of insulation layer 3 becomes trench as shown in FIG. 1D. This phenomenon is xe2x80x98Erosionxe2x80x99.
FIG. 2 shows the above-described phenomenon on graph. In FIG. 2, the horizontal axis represents polishing time, and the vertical axis represents distance (height) from a back surface of the substrate to a surface of the substrate. The surface of the substrate before starting of polishing is approximately flat, and grain-size of plating metal layer 5 placed at the upper part than the barrier metal layer 4 is approximately uniform in any place. For that reason, in the initial stage of start of polishing, polishing of the wiring isolated part and polishing of wiring dense part are progressed with equal speed. Next, when the whole metal plating layer is removed, before the barrier metal layer 4 is exposed (T1 in FIG. 2), after that, polishing becomes polishing of the barrier metal layer 4 and the silicone oxide layer 3, therefore, the polishing speed becomes slow suddenly. On the contrary, in the wiring dense part, since a lot of embedded parts of the metal plating layer 5 exist, polishing speed after xe2x80x98T1xe2x80x99 becomes larger than that of the wiring isolated part according to the reason described above. For that reason, xe2x80x98Erosionxe2x80x99 occurs.
As described above, when xe2x80x98Erosionxe2x80x99 occurs, flatness of substrate surface deteriorates. The deterioration of the flatness becomes more conspicuous in the case of multi-layer structure, thus it causes problem that short circuit of wiring part and so forth occur. Further, when it forms embedded wiring, section area becomes small, problem occurs that wiring resistance becomes large.
In view of the foregoing, it is an object of the present invention, in order to overcome the above-mentioned problems to provide manufacturing method of a semiconductor device including wiring dense part (dense pattern) and wiring isolated part, which manufacturing method enables occurrence of an xe2x80x98Erosionxe2x80x99 to be prevented.
It is another object of the present invention to provide manufacturing method of a semiconductor device including wiring dense part (dense pattern) and wiring isolated part, which manufacturing method enables occurrence of a micro-scratch to be prevented.
According to a first aspect of the present invention, in order to achieve the above mentioned object, there is provided a manufacturing method of a semiconductor device which comprises the steps of a first manufacturing step in which it forms insulation layer on a semiconductor substrate, and it forms a plurality of trench-parts at prescribed points on the insulation layer, before it forms metal plating layer on the whole surface so as to embed the plurality of trench-parts, a second manufacturing step for implementing annealing so as to cause grain-size of metal plating layer in a dense pattern where the trench-part is formed densely to be smaller than grain-size of metal plating layer in a pattern except for the dense pattern, and a third manufacturing step for causing surface of substrate to be flat while polishing the metal plating layer and the insulation layer.
In general, metal material which is subjected to plating has structure which small size grain is gathered to be formed. When the metal plating layer undergoes annealing, grain-size of the grain increases while facing in the constant direction. Thus resistance value of plating layer decreases due to the fact that the grain-size increases, with the result that characteristic as conductive film is stabilized preferably.
The conventional annealing process after plating, for instance, in the case of copper plating, the annealing has been implemented in high temperature of more than 300xc2x0 C. for enhancing productivity. Under such the condition, grain is growing with uniform speed all over the surface in spite of shape of pattern for forming plating layer. Consequently, in the conventional process, there does not occur difference in grain-size between dense pattern of trench-part and another pattern except for dense-pattern. To the contrary, in the present invention, a second manufacturing step implements annealing in such a way that the grain-size of the metal plating layer in the dense pattern in which the trench-part is formed densely becomes smaller than the grain-size of the metal plating layer in the pattern except for the dense pattern.
According to an investigation of the present invention, when it causes the grain-size of metal plating layer to be small, it is capable of suppressing speed of polishing by xe2x80x98CMPxe2x80x99 and so forth effectively. For that reason, polishing of the plating layer in the dense pattern is suppressed by implementing annealing according to the above-described method, thus occurrence of xe2x80x98Erosionxe2x80x99 can be prevented.
According to a second aspect of the present invention, there is provided a manufacturing method of semiconductor device which comprises the steps of a first manufacturing step in which it forms insulation layer on a semiconductor substrate, and it forms a plurality of trench-parts at prescribed points on the insulation layer, before it forms metal plating layer on the whole surface so as to embed the plurality of trench-parts, a second manufacturing step for implementing annealing in such a condition that the step causes temperature of substrate to be about 70xc2x0 C. to about 200xc2x0 C., and a third manufacturing step for causing surface of substrate to be flat while polishing the metal plating layer and the insulation layer.
In the present invention, the second manufacturing step implements annealing with temperature of 70 to 200xc2x0 C. Formerly, annealing of the metal plating layer is implemented in short time of degree of 30 minutes with high temperature of more than 300xc2x0 C. for enhancing productivity. In the present invention, lower temperature than 300xc2x0 C. is dared to be selected. According to the selection, it is capable of obtaining effect which is not known formerly that it enables the grain-size of the metal plating layer formed on dense pattern to be small selectively. Namely, the method of the present invention enables the grain in pattern isolated part to grow while suppressing grain-growth of the metal plating layer in the dense pattern. FIG. 5 shows schematic status in which the grain of the metal plating layer in the dense pattern is formed selectively in small size. It is not clear the reason why such phenomenon occurs. However, when annealing is implemented in such the low temperature range described above, it is conjectured that the grain is easy to undergo influence of shape factor of plating growth surface. Namely, in the wiring dense part (dense pattern) in FIG. 5, it is conjectured that large grain-size is not obtained, because since a plurality of trench-parts are formed, grain grows from various kinds of direction. The inventors have discovered that when annealing is implemented under the condition that substrate-temperature is set to less than 200xc2x0 C., the above-described phenomenon occurs peculiarly, thus the present invention have been perfected.
In the present invention, at the time of annealing, substrate-temperature is set to less than 200xc2x0 C., more preferably less than 150xc2x0 C. According to such the setting of temperature, it enables the grain-size of the metal plating layer in the dense pattern to be small selectively. Further, at the time of annealing, substrate-temperature is set to more than 70xc2x0 C., more preferably more than 80xc2x0 C. According to such the setting of temperature, it is capable of suppressing increase of annealing time. When the substrate-temperature at the time of annealing is set to 70 to 200xc2x0 C., annealing time is set to 30 to 120 minutes.
For instance, in the case of copper plating, when the substrate-temperature is set to 70 to 200xc2x0 C., in the dense pattern, small grain of degree of average particle diameter 20 to 200 nm grow. On the other hand, in the area in which embedded wiring of isolated copper plating layer or isolated connection hole is provided, or in the area there does not exist copper plating layer, great grain of degree of average particle diameter of 500 to 10000 nm grow.
According to a third aspect of the present invention, there is provided a manufacturing method of a semiconductor device which comprises the steps of a first manufacturing step in which it forms insulation layer on a semiconductor substrate, and it forms a plurality of trench-parts at prescribed points on the insulation layer, before it forms metal plating layer on the whole surface so as to embed the plurality of trench-parts, a second manufacturing step for implementing annealing under the condition that xe2x80x98Vickers hardnessxe2x80x99 of the metal plating layer is about 120 Hv to about 180 Hv in a dense pattern where the trench-part is formed densely, while xe2x80x98Vickers hardnessxe2x80x99 of the metal plating layer is about 60 Hv to about 110 Hv in a pattern except for the dense pattern, and a third manufacturing step for causing surface of substrate to be flat while polishing the metal plating layer and the insulation layer.
The xe2x80x98Vickers hardnessxe2x80x99 is one kind of definition of hardness. The xe2x80x98Vickers hardnessxe2x80x99 is measured using xe2x80x98Vickers hardnessxe2x80x99 tester. The xe2x80x98Vickers hardnessxe2x80x99 tester squeezes quadrangular pyramid diamond with vertical angle of 136 degrees in surface of test piece while adding external force. It measures area of depression after removing external force, thus obtaining hardness number depend on average pressure in every unit area of the depression. In the second manufacturing step of the third aspect of the present invention, annealing is implemented in such a way that xe2x80x98Vickers hardnessxe2x80x99 becomes 120 to 180 Hv in the dense pattern where trench-part is formed densely, while xe2x80x98Vickers hardnessxe2x80x99 becomes 60 to 110 Hv in the area except for the dense pattern. Namely, annealing is implemented in such a way that hardness of the metal plating layer in the dense pattern becomes higher than the hardness of the metal plating layer in the area except for the dense pattern. According to such annealing, it is capable of suppressing polishing of the dense pattern, thus it is capable of suppressing occurrence of xe2x80x98Erosionxe2x80x99.
Above-described range of xe2x80x98Vickers hardnessxe2x80x99 can be realized by implementing annealing, for instance, with the substrate-temperature as 70 to 200xc2x0 C. In the case of copper plating, when the substrate-temperature is set to 70 to 200xc2x0 C. at the time of annealing, degree of average particle diameter 20 to 200 nm of small grain grow in the dense pattern, while in the area in which copper wiring and so forth are provided in isolated condition, or in the area in which there does not exist wiring pattern, degree of average particle diameter of 500 to 10000 nm of large grain grow. The xe2x80x98Vickers hardnessxe2x80x99 of plating layer consisting of the above-described small grain becomes 120 to 180 Hv, while the xe2x80x98Vickers hardnessxe2x80x99 of plating layer consisting of the above-described large grain becomes 60 to 110 Hv.
In the present invention, it is preferable that the xe2x80x98Vickers hardnessxe2x80x99 in the dense pattern is set to 130 to 180 Hv, while the xe2x80x98Vickers hardnessxe2x80x99 in the area except for the dense pattern is set to 60 to 100 Hv. According to such the setting, it is capable of further suppressing occurrence of the xe2x80x98Erosionxe2x80x99.
According to a fourth aspect of the present invention, in any of the first to the third aspects, there is provided a manufacturing method of a semiconductor device, wherein the metal plating layer is copper system metal layer.
According to a fifth aspect of the present invention, in any of the first to the fourth aspects, there is provided a manufacturing method of a semiconductor device, wherein formation of the metal plating layer in the first manufacturing step is implemented according to an electrolytic plating method in which a pulse power source is employed, and whose current value is in a range of about 2 to about 5 A/dm2.
According to a sixth aspect of the present invention, in any of the first to the fifth aspects, there is provided a manufacturing method of a semiconductor device, wherein a third manufacturing step for causing surface of substrate to be flat while polishing the metal plating layer and the insulation layer is implemented using xe2x80x98CMPxe2x80x99 (Chemical Mechanical Polishing).
According to seventh aspect of the present invention, in any of the first to the sixth aspects, there is provided a manufacturing method of a semiconductor device, wherein xe2x80x98applied pressurexe2x80x99 is set to about 1 to about 10 psi at the time when said xe2x80x98CMPxe2x80x99 (Chemical Mechanical Polishing) is implemented.